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| KSZ8021RNL / ksz8031rnl 10base-t/100base-tx phy with rmii support linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com august 2010 m9999-082710-1.0 general description the ksz8031rnl is a single-supply 10base-t/100base- tx ethernet physical layer transceiver for transmission and reception of data over standard cat-5 unshielded twisted pair (utp) cable. the ksz8031rnl is a highly-integrated, compact solution. it reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs, by integrating a low noise regulator to supply the 1.2v core, and by offering 1.8/2.5/3.3v digital i/o interface support. the ksz8031rnl offers the reduced media independent interface (rmii) for direct connection to rmii-compliant macs in ethernet processors and switches. as the power-up default, the ksz8031rnl uses a 25mhz crystal to generate all required clocks, including the 50mhz rmii reference clock output for the mac. the KSZ8021RNL is the version that takes in the 50mhz rmii reference clock as the power-up default. to facilitate system bring-up and debugging in production testing and in product deployment, parametric nand tree support enables fault detection between ksz8031rnl i/os and board, while micrel?s linkmd ? tdr-based cable diagnostics permit identification of faulty copper cabling. the ksz8031rnl and KSZ8021RNL are available in 24- pin, lead-free qfn packages (see ordering information ). data sheets and support documentation can be found on micrel?s web site at: www.micrel.com . features ? single-chip 10base-t/100base-tx ieee 802.3 compliant ethernet transceiver ? rmii v1.2 interface support with 50mhz reference clock output to mac, and option to input 50mhz reference clock ? rmii back-to-back mode suppo rt for 100mbps copper repeater or media converter ? mdc/mdio management interface for phy register configuration ? programmable interrupt output ? led outputs for link and activity status indication ? on-chip termination resistors for the differential pairs ? baseline wander correction ? hp auto mdi/mdi-x for reliable detection and correction for straight-thr ough and crossover cables with disable and enable option ? auto-negotiation to automatically select the highest link- up speed (10/100 mbps) and duplex (half/full) ? power down and power saving modes ? linkmd ? tdr-based cable diagnostics for identification of faulty copper cabling ? parametric nand tree support for fault detection between chip i/os and board ____________________________________________________________________________________________________________ functional diagram
micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 2 m9999-082710-1.0 more features ? loopback modes for diagnostics ? single 3.3v power supply with vdd i/o options for 1.8v, 2.5v, or 3.3v ? built-in 1.2v regulator for core ? available in 24-pin (4mm x 4mm) qfn package applications ? game console ? ip phone ? ip set-top box ? ip tv ? lom ? printer ordering information part number temperature range package lead finish description KSZ8021RNL 0c to 70c 24-pin qfn pb-free rmii with 50mhz clock in put (power-up default), commercial temperature KSZ8021RNLi (1) ? 40c to 85c 24-pin qfn pb-free rmii with 50mhz clock in put (power-up default), industrial temperature ksz8031rnl 0c to 70c 24-pin qfn pb-free rmii with 25mhz crystal/clock input and 50mhz rmii ref_clk output (power-up default), commercial temperature ksz8031rnli (1) ? 40c to 85c 24-pin qfn pb-free rmii with 25mhz crystal/clock input and 50mhz rmii ref_clk output (power-up default), industrial temperature note: 1. contact factory for lead time. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 3 m9999-082710-1.0 revision history revision date summary of changes 1.0 8/16/10 data sheet created. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 4 m9999-082710-1.0 contents general desc ription ............................................................................................................ .................................................. 1 features ....................................................................................................................... .......................................................... 1 functional diagram............................................................................................................. .................................................. 1 applicat ions................................................................................................................... ........................................................ 2 ordering info rmation ........................................................................................................... ................................................. 2 revision hi story............................................................................................................... ..................................................... 3 contents....................................................................................................................... .......................................................... 4 list of figures........................................................................................................................................................................ 6 list of tables ................................................................................................................. ........................................................ 7 pin configuration ? ks z8021rnl / ksz8031rnl.................................................................................... .......................... 8 pin description ? ksz8 021rnl / ksz8031rnl ...................................................................................... ........................... 9 strapping options ? ksz 8021rnl / ks z8031rnl .................................................................................... ...................... 11 functional description: 10base -t/100base-tx transceiver ....................................................................... .................. 12 100base-tx transm it....................................................................................................................................................... 12 100base-tx receive............................................................................................................. ........................................... 12 10base-t tr ansmit ........................................................................................................................................................... 12 10base-t re ceive ............................................................................................................................................................ 13 scrambler/de-scrambler (100base-tx only)....................................................................................... ............................. 13 pll clock synthesizer.......................................................................................................... ............................................ 13 auto-negot iation ............................................................................................................... ................................................ 13 rmii data in terface............................................................................................................ .................................................. 15 rmii signal de finition ......................................................................................................... .............................................. 15 reference cloc k (ref_clk) ...................................................................................................... ................................. 15 transmit e nable (t xen) .............................................................................................................................................. 15 transmit data [1 :0] (txd[1:0]) ................................................................................................. .................................... 15 carrier sense/receive data valid (crs_dv)...................................................................................... ........................ 15 receive data [1 :0] (rxd[1:0]) .................................................................................................. .................................... 16 receive error (rxer) ........................................................................................................... ....................................... 16 collision de tection............................................................................................................ ............................................ 16 rmii signal diagram ? for ksz8021/31rnl........................................................................................ .............................. 16 rmii ? 25mhz clock mode........................................................................................................ ....................................... 16 rmii ? 50mhz clock mode........................................................................................................ ....................................... 17 back-to-back mode ? 100mbps copp er repeater / me dia converter.................................................................. .......... 18 rmii back-to- back mode......................................................................................................... ......................................... 18 mii management (m iim) interface................................................................................................ ....................................... 19 interrupt (intrp) .............................................................................................................. ................................................... 19 hp auto md i/mdi-x .............................................................................................................. ............................................... 19 straight cable ................................................................................................................. .................................................. 20 crossover cable ................................................................................................................ ............................................... 20 linkmd ? cable dia gnostics.............................................................................................................. .................................. 21 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 5 m9999-082710-1.0 nand tree support .............................................................................................................. .............................................. 21 nand tree i/o testing..................................................................................................................................................... 22 power management ............................................................................................................... ............................................. 22 power saving m ode.............................................................................................................. ............................................ 22 energy detect po wer down mode .................................................................................................. ................................. 22 power down mode ................................................................................................................ ........................................... 22 slow oscilla tor mode ........................................................................................................... ............................................. 23 reference circuit for powe r and ground connect ions ............................................................................. ..................... 23 register map................................................................................................................... ..................................................... 24 register de scription ........................................................................................................... ................................................ 24 register descript ion (continued)............................................................................................... ....................................... 25 register descript ion (continued)............................................................................................... ....................................... 26 register descript ion (continued)............................................................................................... ....................................... 27 register descript ion (continued)............................................................................................... ....................................... 28 register descript ion (continued)............................................................................................... ....................................... 29 register descript ion (continued)............................................................................................... ....................................... 30 register descript ion (continued)............................................................................................... ....................................... 31 register descript ion (continued)............................................................................................... ....................................... 32 absolute maximum ratings (1) ............................................................................................................................................ 33 operating ratings (2) ............................................................................................................................................................ 33 electrical characteristics (3) ................................................................................................................................................ 33 electrical characteristics (3) (continued) ................................................................................................................... ........ 34 timing di agrams ................................................................................................................ ................................................. 35 rmii timing.................................................................................................................... ................................................... 35 auto-negotiati on timi ng ........................................................................................................ ........................................... 36 mdc/mdio timing ................................................................................................................ ........................................... 37 reset timing................................................................................................................... .................................................. 38 reset ci rcuit .................................................................................................................. ...................................................... 39 reference circuit fo r led stra pping pin........................................................................................ .................................. 40 magnetics speci fication ........................................................................................................ ............................................. 41 reference clock ? conne ction and se lection..................................................................................... ............................. 41 package info rmation............................................................................................................ ............................................... 43 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 6 m9999-082710-1.0 list of figures figure 1. auto-negotiation flow chart......................................................................................... ........................................ 14 figure 2. ksz8021/31rnl rmii inte rface (rmii ? 25mh z clock mode) .............................................................. .............. 16 figure 3. ksz8021/31rnl rmii inte rface (rmii ? 50mh z clock mode) .............................................................. .............. 17 figure 4. ksz8021/31rn l and ksz8041ftl rmii back-t o-back media converter ...................................................... .... 18 figure 5. typical stra ight cable connection ................................................................................... .................................... 20 figure 6. typical cros sover cable connection .................................................................................. ................................. 20 figure 7. ksz8021/31rnl power and ground connections .......................................................................... .................... 23 figure 8. rmii timing ? da ta received from rmii ............................................................................... ............................... 35 figure 9. rmii timing ? data input to rmii .................................................................................... ..................................... 35 figure 10. auto-negotiation fa st link pulse (flp) ti ming ...................................................................... ........................... 36 figure 11. mdc/ mdio timing.................................................................................................... .......................................... 37 figure 12. re set timing....................................................................................................................................................... 38 figure 13. recommen ded reset circuit.......................................................................................... .................................... 39 figure 14. recommended reset circuit for interfacing with cpu/ fpga rese t output............................................... ....... 39 figure 15. reference circui ts for led st rapping pin ........................................................................... ............................... 40 figure 16. 25mhz crystal / oscillator reference cl ock connection .............................................................. ..................... 41 figure 17. 50mhz oscillator reference clock connection ........................................................................ ......................... 42 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 7 m9999-082710-1.0 list of tables table 1. rmii si gnal description.............................................................................................. ............................................ 15 table 2. rmii signal connection for rmii back- to-back mode (100 base-tx copper repeater) ...................................... 18 table 3. mii management fram e format ? fo r ksz8021/31 rnl........................................................................................ 19 table 4. mdi/mdi- x pin definition ............................................................................................. .......................................... 20 table 5. nand tree test pi n order ? for ksz8021/ 31rnl ......................................................................... ...................... 21 table 6. ksz8021/31rnl po wer pin desc ription .................................................................................. ............................. 23 table 7. rmii timing parameters ? ksz8021/31rnl (25mhz input to xi pin, 50mhz output from ref_clk pin)........... 35 table 8. rmii timing parameters ? ksz8021/31rnl (50mhz i nput to xi pin)....................................................... ............ 35 table 9. auto-negotiation fast link pulse (flp) timing parameters ............................................................. .................... 36 table 10. mdc/mdio timing pa rameters .......................................................................................... ................................. 37 table 11. reset timing parameters ............................................................................................. ....................................... 38 table 12. magnetics selection criteria ........................................................................................ ........................................ 41 table 13. qualified singl e port 10/100 magnetics.............................................................................. ................................. 41 table 14. 25mhz crystal / refe rence clock selection criteria .................................................................. ......................... 42 table 15. 50mhz oscillator / refe rence clock sele ction cr iteria ............................................................... ........................ 42 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 8 m9999-082710-1.0 pin configuration ? KSZ8021RNL / ksz8031rnl 24-pin (4mm x 4mm) qfn micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 9 m9999-082710-1.0 pin description ? KSZ8021RNL / ksz8031rnl pin number pin name type (1) pin function 1 vdd_1.2 p 1.2v core v dd (power supplied by KSZ8021RNL / ksz8031rnl) decouple with 2.2uf and 0. 1uf capacitors-to-ground. 2 vdda_3.3 p 3.3v analog v dd . 3 rxm i/o physical receive or transmit signal (- differential) 4 rxp i/o physical receive or transmit signal (+ differential) 5 txm i/o physical transmit or receive signal (- differential) 6 txp i/o physical transmit or receive signal (+ differential) 7 xo o crystal feedback ? for 25 mhz crystal this pin is a no connect if oscillator or external clock source is used. 8 xi i rmii ? 25mhz mode: 25mhz +/-50ppm crystal / oscillator / external clock input rmii ? 50mhz mode: 50mhz +/-50ppm oscillator / external clock input for unmanaged mode (power-up default setting), KSZ8021RNL takes in the 50mhz clock on this pin. ksz8031rnl takes in the 25mhz crystal / clock on this pin. after power-up, both the KSZ8021RNL and ksz8031rnl can be programmed via phy register 1fh bit [7] to either the 25mhz mode or 50mhz mode. see also ref_clk (pin 16) description. 9 rext i set physical transmit output current connect a 6.49k resistor-to-ground on this pin. 10 mdio i/o management interface (mii) data i/o this pin has a weak pull-up, is open drain like, and requires an external 1.0k ? pull- up resistor. 11 mdc i management interface (mii) clock input this clock pin is synchronous to the mdio data pin. 12 rxd1 ipd/o rmii receive data output[1] (2) 13 rxd0 ipu/o rmii receive data output[0] (2) 14 vddio p 3.3v, 2.5v or 1.8v digital v dd 15 crs_dv / phyad[1:0] ipd/o rmii mode: carrier sense/receive data valid output / config mode: the pull-up/pull-down value is latched as phyad[1:0] at the de-assertion of reset. see ?strapping options? section for details. 16 ref_clk ipd/o rmii ? 25mhz mode: this pin provides t he 50mhz rmii reference clock output to the mac. rmii ? 50mhz mode: this pin is a no connect. for unmanaged mode (power-up default setting), KSZ8021RNL is in rmii ? 50mhz mode and does not use this pin. ksz8031rnl is in rmii ? 25mhz mode and outputs the 50mhz rmii reference clock on this pin. after power-up, both KSZ8021RNL and ksz8031rnl can be programmed via phy register 1fh bit [7] to either 25mhz mode or 50mhz mode. see also xi (pin 8) description. 17 rxer ipd/o rmii receive error output 18 intrp ipu/opu interrupt output: progra mmable interrupt output this pin has a weak pull-up, is open drain like, and requires an external 1.0k ? pull- up resistor. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 10 m9999-082710-1.0 pin description ? KSZ8021RNL / ksz8031rnl (continued) pin number pin name type (1) pin function 19 txen i rmii transmit enable input 20 txd0 i rmii transmit data input[0] (3) 21 txd1 i/o rmii transmit data input[1] (3) nand tree mode: nand tree output pin 22 gnd gnd ground 23 led0 / anen_speed ipu/o led output: programmable led0 output / config mode: latched as auto-negotia tion enable (register 0h, bit [12]) and speed (register 0h, bit [13]) at the de-assertion of reset. see ?strapping options? section for details. the led0 pin is programmable via register 1fh bits [5:4], and is defined as follows. led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definition no link high off link low on led mode = [10], [11] reserved 24 rst# i chip reset (active low) paddle gnd gnd ground notes: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipu/o = input with internal pull-up (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipu/opu = input with internal pull-up (s ee electrical characteristics for value) during power-up/reset; output pin with intern al pull-up (see electrical characteristics for value) otherwise. 2. rmii rx mode: the rxd[1:0] bits are synchronous with the 50mhz rmii reference clock. for each clock period in which crs_dv is asserted, two bits of recovered data are sent by the phy to the mac. 3. rmii tx mode: the txd[1:0] bits are synchronous with the 50mhz rmii reference clock . for each clock period in which txen is asserted, two bits of data are received by the phy from the mac. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 11 m9999-082710-1.0 strapping options ? ks z8021rnl / ksz8031rnl pin number pin name type (1) pin function 15 phyad[1:0] ipd/o the phy address is latched at the de-asserti on of reset and is configurable to either one of the following two values: pull-up = phy address is set to 00011b (0x3h) pull-down (default) = phy address is set to 00000b (0x0h) phy address bits [4:2] are set to ?000? by default. 23 anen_speed ipu/o auto-negotiation enable and speed mode pull-up (default) = enable auto-negotiation and set 100mbps speed pull-down = disable auto-negotiation and set 10mbps speed at the de-assertion of reset, this pin value is latched into register 0h bit [12] for auto- negotiation enable/disable, register 0h bit [13] for the speed select, and register 4h (auto-negotiation advertisement) for the speed capability support. note: 1. ipu/o = input with internal pull-up (see electrical charac teristics for value) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (see electrical characteristics for value) during power-up/reset; output pin otherwise. the phyad[1:0] strap-in pin is latched at the de-assertion of re set. in some systems, the rmii mac receive input pin may drive high/low during power-up or reset, and consequently cause the phyad[1:0] strap-in pin, a shared pin with the rmii crs_dv signal, to be latched to the unintended high/low states. in this case, an external pull-up (4.7k) or pull-down (1.0k) should be added on the phyad[1:0] stra p-in pin to ensure the intended value is strapped-in correctly. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 12 m9999-082710-1.0 functional description: 10 base-t/100base-tx transceiver the ksz8031rnl is an integrated single 3.3v supply fast et hernet transceiver. it is fully compliant with the ieee 802.3 specification. it reduces boar d cost and simplifies board layout by using on-chip termination resistors for the two differential pairs and by integrating t he regulator to supply the 1.2v core. on the copper media side, the ksz8031rnl supports 10base- t and 100base-tx for transmission and reception of data over a standard cat-5 unshielded twis ted pair (utp) cable, and hp auto mdi/mdi-x for reliable detection of and correction for straight-through and crossover cables. on the mac side, the ksz8031rnl provides the reduced media independent interface (rmii) for direct connection with rmii-compliant ethernet mac processors and switches. the mii management bus option gives the mac processor co mplete access to the ksz8031rnl control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll for phy status change. as the power-up default, the ksz8031rnl uses a 25mhz crystal to generate all required clocks, including the 50mhz rmii reference clock output for the mac. the KSZ8021RNL is the version which takes in the 50mhz rmii reference clock as the power-up default. the ksz8021/31rnl is used to refer to both KSZ8021RNL and ksz8031rnl versions in this data sheet. 100base-tx transmit the 100base-tx transmit function perfor ms parallel-to-serial conversion, 4b/5b encoding, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b /5b coding and followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transm itted in mlt3 current output. the output current is set by an external 6.49k 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and co mplies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-shaped 10base-t output is also incorporated into the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function performs adaptive equalization, dc restoration, mlt3-to-nr zi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalizati on filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based upon comparisons of incoming signal strength against some known cabl e characteristics, and then tunes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and dat a conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 1 25mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this si gnal is sent through the de-sc rambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data to the mac. 10base-t transmit the 10base-t drivers are incorporated wi th the 100base-tx drivers to allow for transmission using the same magnetic. the drivers perform internal wave-shaping and pre-emphasis, and output 10base-t signals with a typical amplitude of 2.5v peak. the 10base-t signals have harmonic contents that are at least 27db below the fundamental frequency when driven by an all-ones manchester-encoded signal. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 13 m9999-082710-1.0 10base-t receive on the receive side, input buffer and level detecting squelch ci rcuits are employed. a differential input receiver circuit and a pll performs the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400 mv or with short pulse widths to prevent noise at the rxp and rxm inputs from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8021/31rnl decodes a data frame. t he receive clock is kept active during idle periods in between data reception. scrambler/de-scrambler (100base-tx only) the scrambler is used to spread the power spectrum of t he transmitted signal to reduce emi and baseline wander, and the de-scrambler is needed to recover the scrambled signal. pll clock synthesizer the ksz8021/31rnl in rmii ? 25mhz clock mode generates all inte rnal clocks and all external clocks for system timing from an external 25mhz crystal, oscill ator, or reference clock. for the ksz8021/31rnl in rmii ? 50mhz clock mode, these clocks are generated from an external 50mhz oscillator or system clock. auto-negotiation the ksz8021/31rnl conforms to the auto- negotiation protocol, defined in clause 28 of the ieee 802.3 specification. auto-negotiation allows utp (unshielded twisted pair) link par tners to select the highest common mode of operation. during auto-negotiation, link partners adv ertise capabilities across the utp link to each other, and then compare their own capabilities with those they received from their link partne rs. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest priority. ? priority 1: 100base-tx, full-duplex ? priority 2: 100base-tx, half-duplex ? priority 3: 10base-t, full-duplex ? priority 4: 10base-t, half-duplex if auto-negotiation is not supported or the ksz8021/31rnl link partner is forced to bypass auto-negotiation, then the ksz8021/31rnl sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the ksz8021/31rnl to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. auto-negotiation is enabled by either ha rdware pin strapping (anen_speed, pin 23) or software (register 0h, bit [12]). by default, auto-negotiation is enabled after power-up or ha rdware reset. afterwards, auto-negotiation can be enabled or disabled by register 0h, bit [12]. if auto-negot iation is disabled, the speed is set by register 0h, bit [13], and the duplex i s set by register 0h, bit [8]. the auto-negotiation link up process is shown in figure 1. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 14 m9999-082710-1.0 figure 1. auto-negotiation flow chart micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 15 m9999-082710-1.0 rmii data interface the reduced media independent interface (rmii) specifies a low pin count media independent interface (mii). it provides a common interface between physical layer and mac layer devices, and has the following key characteristics: ? pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, 1 pin for the 50mhz reference clock). ? 10mbps and 100mbps data rates are supported at both half and full duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 2-bit wide, a dibit. rmii signal definition the following table describes the rmii signals. refer to rmii specification v1.2 for detailed information. rmii signal name direction (with respect to phy, ksz8021/31rnl signal) direction (with respect to mac) description ref_clk output (25mhz clock mode) / micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 16 m9999-082710-1.0 so long as carrier detection criteria are met, crs_dv remains asserted continuously from the first recovered dibit of the frame through the final recovered dibit, and it is negated prior to the first ref_clk that follows the final dibit. the data on rxd[1:0] is considered valid once crs_dv is asserted. however, since the assertion of crs_dv is asynchronous relative to ref_clk, the data on rxd[1:0] is " 00" until proper receive signal decoding takes place. receive data [1:0] (rxd[1:0]) rxd[1:0] transitions synchronously with respect to ref_clk. for each clock period in which crs_dv is asserted, rxd[1:0] transfers two bits of recovered data from the phy. rxd[1:0] is "00" to indicate idle when crs_dv is de-ass erted. values other than ?00? on rxd[1:0] while crs_dv is de- asserted are ignored by the mac. receive error (rxer) rxer is asserted for one or more ref_clk periods to indica te that a symbol error (e.g., a coding error that a phy is capable of detecting, and that may otherwise be undetect able by the mac sub-layer) wa s detected somewhere in the frame presently being transferred from the phy. rxer transitions synchronously with respect to ref_clk. while crs_dv is de-asserted, rxer has no effect on the mac. collision detection the mac regenerates the col signal of the mii from txen and crs_dv. rmii signal diagram ? for ksz8021/31rnl the ksz8021/31rnl rmii pin connections to the mac are sh own in the following figures for rmii ? 25mhz clock mode and rmii ? 50mhz clock mode. rmii ? 25mhz clock mode the ksz8031rnl is configured to rmii ? 25mhz clock mode afte r it is powered up or hardware reset with the following: ? a 25mhz crystal connected to xi, xo (pins 8, 7), or an external 25mhz cloc k source (oscillator) connected to xi the KSZ8021RNL is configured optionally to rmii ? 25mhz clock mode after it is powered up or hardware reset and software programmed with the following: ? a 25mhz crystal connected to xi, xo (pins 8, 7), or an external 25mhz cl ock source (oscillator) connected to xi ? register 1fh, bit [7] programmed to ?0? to select rmii ? 25mhz clock mode figure 2. ksz8021/31rnl rmii interface (rmii ? 25mhz clock mode) micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 17 m9999-082710-1.0 rmii ? 50mhz clock mode the KSZ8021RNL is configured to rmii ? 50mhz clock mode afte r it is powered up or hardware reset with the following: ? an external 50mhz clock source (oscillator) connected to xi (pin 8) the ksz8031rnl is configured optionally to rmii ? 50mhz clock mode after it is powered up or hardware reset and software programmed with the following: ? an external 50mhz clock source (oscillator) connected to xi (pin 8) ? register 1fh, bit [7] programmed to ?1? to select rmii ? 50mhz clock mode figure 3. ksz8021/31rnl rmii interface (rmii ? 50mhz clock mode) micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 18 m9999-082710-1.0 back-to-back mode ? 10 0mbps copper repeater / media converter two ksz8021/31rnl devices can be connected back-to-ba ck to form a managed 100base-tx copper repeater. a ksz8021/31rnl and a ksz8041ftl can be connected back-to-ba ck to provide a managed media converter solution. media conversion is between 100base-tx copper and 100base-fx fiber. on the copper side, link up at 10base-t is not allowed, and is blocked during auto-negotiation. figure 4. ksz8021/31rnl and ksz8041ftl rmii back-to-back media converter rmii back-to-back mode in rmii back-to-back mode, a ksz8021/31rnl interfaces with another ksz8021/31rnl, or a ksz8041ftl to provide a 100mbps copper repeater, or media converter solution, respectively. the ksz8021/31rnl devices are configured to rmii back-to-back mode after they are powered up or hardware reset and software programmed with the following: ? a common 50mhz reference clock connected to xi (pin 8) ? register 1fh, bit [7] programmed to ?1? to select rmii ? 50mhz clock mode for ksz8031rnl (KSZ8021RNL is set to rmii ? 50mhz clock mode as the default after power up or hardware reset) ? register 16h, bits [6] and [1] programmed to ?1? and ?1?, respectively, to enable rmii back-to-back mode. ? rmii signals connected as shown in the following table. ksz8021/31rnl (100b ase-tx copper) [device 1] ksz8021/31rnl (100b ase-tx copper) [device 2] pin name pin number pin type pin name pin number pin type crs_dv 15 output txen 19 input rxd1 12 output txd1 21 input rxd0 13 output txd0 20 input txen 19 input crs_dv 15 output txd1 21 input rxd1 12 output txd0 20 input rxd0 13 output table 2. rmii signal connection for rmii back-to-back mode (100b ase-tx copper repeater) micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 19 m9999-082710-1.0 mii management (miim) interface the ksz8021/31rnl supports th e ieee 802.3 mii management interface, also known as the management data input / output (mdio) interface. this interface enables upper-layer device, like a mac proc essor, to monitor and control the state of the ksz8021/31rnl. an external device with miim capability is used to read the phy status and/or configure the phy settings. further details on the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates t he clock line (mdc) and the data line (mdio). ? a specific protocol that operates across the aforementioned physical connection that allows the external controller to communicate with one or more phy devices. ? a set of 16-bit mdio registers. registers [0:8] are standard registers, and their func tions are defined per the ieee 802.3 specification. the additional regi sters are provided for expanded functio nality. see ?register map? section for details. the ksz8021/31rnl supports only two unique phy addresses, 0x0h and 0x3h. the phyad[1:0] strapping pin is used to select either 0x0h or 0x3h as the unique phy address for the ksz8021/31rnl device. table 3 shows the mii management frame format for the ksz8021/31rnl. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 000aa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 000aa rrrrr 10 dddddddd_dddddddd z table 3. mii management frame format ? for ksz8021/31rnl interrupt (intrp) the intrp (pin 18) is an optional interrupt signal that is used to inform the external controlle r that there has been a status update to the ksz8021/31rnl phy register. register 1bh, bits [ 15:8] are the interrupt control bits to enable and disable the conditions for asserting the intrp signal. register 1bh, bi ts [7:0] are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt stat us bits are cleared after reading register 1bh. register 1fh, bit 9 sets the interrupt level to acti ve high or active low. the default is active low. the mii management bus option gives the mac processor co mplete access to the ksz8021/31rnl control and status registers. additionally, an interrupt pi n eliminates the need for the processor to poll the phy for status change. hp auto mdi/mdi-x the hp auto mdi/mdi-x configuration eliminates the confusio n of whether to use a straight cable or a crossover cable between the ksz8021/31rnl and its link partner. this feature allows the ksz8021/31rnl to use either type of cable to connect with a link partner that is in either mdi or mdi- x mode. the auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the ksz8021/31rnl accordingly. hp auto mdi/mdi-x is enabled by default. it is disabled by writing a one to regist er 1fh, bit [13]. mdi and mdi-x mode is selected by register 1fh, bit [14] if hp auto mdi/mdi-x is disabled. an isolation transformer with symmetrical transmit and re ceive data paths is recommended to support auto mdi/mdi-x. the ieee 802.3 standard defines mdi and mdi-x in table 4. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 20 m9999-082710-1.0 mdi mdi-x rj-45 pin signal rj-45 pin signal 1 tx+ 1 rx+ 2 tx- 2 rx- 3 rx+ 3 tx+ 6 rx- 6 tx- table 4. mdi/mdi-x pin definition straight cable a straight cable connects a mdi device to a mdi-x device, or a mdi-x device to a mdi device. figure 5 depicts a typical straight cable connection between a nic card (mdi) and a switch, or hub (mdi-x). figure 5. typical straight cable connection crossover cable a crossover cable connects a mdi device to another mdi devic e, or a mdi-x device to another mdi-x device. figure 6 depicts a typical crossover cable connection between two switches or hubs (two mdi-x devices). figure 6. typical crossover cable connection micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 21 m9999-082710-1.0 linkmd ? cable diagnostics the linkmd ? function utilizes time domain reflectometry (tdr) to analyze the cabli ng plant for common cabling problems, such as open circuits, short circuits and impedance mismatches. linkmd ? works by sending a pulse of known amplitude and duration down the mdi or mdi-x pair, and then analyzing the shape of the reflected signal to determine the type of fault. t he time duration for the reflected signal to return provides the approximate distance to the cabling fault. the linkmd ? function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd ? is initiated by accessing register 1dh, the linkmd ? control/status register, in conj unction with register 1fh, the phy control 2 register. the latter register is used to disa ble auto mdi/mdi-x and to select either mdi or mdi-x as the cable differential pair for testing. nand tree support the ksz8021/31rnl provides parametric nand tree support for fault detection between chip i/os and board. the nand tree is a chain of nested nand gates in which each ksz8021/31rnl digital i/o (nand tree input) pin is an input to one nand gate along the chain. at the end of the chain, the txd1 pin provides the output for the nested nand gates. the nand tree test process includes: ? enabling nand tree mode ? pulling all nand tree input pins high ? driving low each nand tree input pin sequentially per the nand tree pin order ? checking the nand tree output to ensure there is a toggl e high-to-low or low-to-high for each nand tree input driven low table 5 lists the nand tree pin order. pin number pin name nand tree description 10 mdio input 11 mdc input 12 rxd1 input 13 rxd0 input 15 crs_dv input 16 ref_clk input 17 rxer input 18 intrp input 19 txen input 20 txd0 input 23 led0 input 21 txd1 output table 5. nand tree test pin order ? for ksz8021/31rnl micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 22 m9999-082710-1.0 nand tree i/o testing the following procedure can be used to check for faults on the ksz8021/31rnl digital i/o pin connections to the board: 1. enable nand tree mode by setting register 16h, bit [5] to ?1?. 2. use board logic to drive all ksz 8021/31rnl nand tree input pins high. 3. use board logic to drive each nand tree input pin, per ksz8021/31rnl nand tree pin order, as follow: a. toggle the first pin (mdio) from high to low, and verify the txd1 pin switch from low to high to indicate that the first pin is connected properly. b. leave the first pin (mdio) low. c. toggle the second pin (mdc) from high to low, and veri fy the txd1 pin switch from high to low to indicate that the second pin is connected properly. d. leave the first pin (mdio) and the second pin (mdc) low. e. toggle the third pin from high to low, and verify the tx d1 pin switch from low to high to indicate that the third pin is connected properly. f. continue with this sequence until all ksz8021/31rnl nand tree input pins have been toggled. each ksz8021/31rnl nand tree input pin must cause the txd1 output pin to toggle high-to-low or low-to-high to indicate a good connection. if the txd1 pin fails to toggle when the ksz8021/31rnl input pin toggles from high to low, then the input pin has a fault. power management the ksz8021/31rnl offers the following power management modes: power saving mode power saving mode is used to reduce the transceiver powe r consumption when the cable is unplugged. it is enabled by writing a one to register 1fh, bit [10], and is in effect when auto-negotiation mode is enabled and cable is disconnected (no link). in this mode, the ksz8021/31rnl turns off all transceiver blocks, except for transmitter, energy detect and pll circuits. by default, power saving mode is disabled after power-up. energy detect power down mode energy detect power down (edpd) mode is used to further reduce the transceiver power consumption when the cable is un-plugged. it is enabled by writing a zero to register 18h, bi t [11], and is in effect when auto-negotiation mode is enabled and cable is disconnected (no link). edpd mode works in conjunction with pll off (set by writing a one to register 10h, bit [4] to turn pll off automatically in edpd mode) to turn off all ksz8021/31rnl transceiver blo cks, except for transmitter and energy detect circuits. further power consumption is achieved by ex tending the time interval in between transmissions of link pulses to check for the presence of a link partner. the periodic transmission of link pulses is needed to ensure two link partners in the same low power state and with auto mdi/mdi-x disabled can wake up when the cable is connected between them. by default, energy detect power down mode is disabled after power-up. power down mode power down mode is used to power down the ksz8021/31rnl device when it is not in use after power-up. it is enabled by writing a one to register 0h, bit [11]. in this mode, the ksz8021/31rnl disables all internal fu nctions, except for the mii management interface. the ksz8021/31rnl exits (disables) power down mode afte r register 0h, bit [11] is set back to zero. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 23 m9999-082710-1.0 slow oscillator mode slow oscillator mode is used to disconnect the input refere nce crystal/clock on xi (pin 8) and select the on-chip slow oscillator when the ksz8021/31rnl device is not in use after power-up. it is en abled by writing a one to register 11h, bit [5]. slow oscillator mode works in conjunction with power down mode to put the ksz8021/31rnl device in the lowest power state with all internal functions disabled, except for the mii management interface. to properly exit this mode and return to normal phy operation, use the fo llowing programming sequence: 1. disable slow oscillator mode by writ ing a zero to register 11h, bit [5]. 2. disable power down mode by writing a zero to register 0h, bit [11]. 3. initiate software reset by writing a one to register 0h, bit [15]. reference circuit for powe r and ground connections the ksz8021/31rnl is a single 3.3v supp ly device with a built-in regulator to supply the 1.2v core. the power and ground connections are shown in figure 7 and table 6 for 3.3v vddio. figure 7. ksz8021/31rnl power and ground connections power pin pin number description vdd_1.2 1 decouple with 2.2uf and 0.1uf capacitors-to-ground. vdda_3.3 2 connect to board?s 3.3v supply through ferrite bead. decouple with 22uf and 0.1uf capacitors-to-ground. vddio 14 connect to board?s 3.3v supply for 3.3v vddio. decouple with 22uf and 0.1uf capacitors-to-ground. table 6. ksz8021/31rnl power pin description micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 24 m9999-082710-1.0 register map register number (hex) description 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto-negotiation advertisement 5h auto-negotiation link partner ability 6h auto-negotiation expansion 7h auto-negotiation next page 8h link partner next page ability 9h reserved 10h digital reserved control 11h afe control 1 12h ? 14h reserved 15h rxer counter 16h operation mode strap override 17h operation mode strap status 18h expanded control 19h ? 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd ? control/status 1eh phy control 1 1fh phy control 2 register description address name description mode (1) default register 0h ? basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.14 loop-back 1 = loop-back mode 0 = normal operation rw 0 0.13 speed select 1 = 100mbps 0 = 10mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1). rw set by anen_speed strapping pin. see ?strapping options? section for details. 0.12 auto- negotiation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process if enabled, auto-negotiation result overrides settings in register 0.13 and 0.8. rw set by anen_speed strapping pin. see ?strapping options? section for details. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 25 m9999-082710-1.0 register descrip tion (continued) address name description mode (1) default register 0h ? basic control 0.11 power down 1 = power down mode 0 = normal operation if software reset (register 0.15) is used to exit power down mode (register 0.11 = 1), two software reset writes (register 0.15 = 1) are required. first write clears power down mode; second write resets chip and re-latches the pin strapping pin values. rw 0 0.10 isolate 1 = electrical isolation of phy from mii 0 = normal operation rw 0 0.9 restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation. this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.8 duplex mode 1 = full-duplex 0 = half-duplex rw 1 0.7 collision test 1 = enable col test 0 = disable col test rw 0 0.6:0 reserved ro 000_0000 register 1h ? basic status 1.15 100base-t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base-tx full duplex 1 = capable of 100mbps full-duplex 0 = not capable of 100mbps full-duplex ro 1 1.13 100base-tx half duplex 1 = capable of 100mbps half-duplex 0 = not capable of 100mbps half-duplex ro 1 1.12 10base-t full duplex 1 = capable of 10mbps full-duplex 0 = not capable of 10mbps full-duplex ro 1 1.11 10base-t half duplex 1 = capable of 10mbps half-duplex 0 = not capable of 10mbps half-duplex ro 1 1.10:7 reserved ro 000_0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto- negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto- negotiation ability 1 = capable to perform auto-negotiation 0 = not capable to perform auto-negotiation ro 1 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 26 m9999-082710-1.0 register descrip tion (continued) address name description mode (1) default 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capabilities registers ro 1 register 2h ? phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1 (hex) ro 0022h register 3h ? phy identifier 2 3.15:10 phy id number assigned to the 19th through 24th bits of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1 (hex) ro 0001_01 3.9:4 model number six bit manufacturer?s model number ro 01_0101 3.3:0 revision number four bit manufacturer?s revision number ro indicates silicon revision register 4h ? auto-negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability. rw 0 4.14 reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved ro 0 4.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric & symmetric pause rw 00 4.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability rw set by anen_speed strapping pin. see ?strapping options? section for details. 4.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability rw set by anen_speed strapping pin. see ?strapping options? section for details. 4.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability rw 1 4.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 27 m9999-082710-1.0 register descrip tion (continued) address name description mode (1) default register 5h ? auto-negot iation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric & symmetric pause ro 00 5.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability ro 0 5.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability ro 0 5.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability ro 0 5.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 0_0001 register 6h ? auto-negotiation expansion 6.15:5 reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto- negotiation able 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability ro 0 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 28 m9999-082710-1.0 register descrip tion (continued) address name description mode (1) default register 7h ? auto-negotiation next page 7.15 next page 1 = additional next page(s) will follow 0 = last page rw 0 7.14 reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic one 0 = logic zero ro 0 7.10:0 message field 11-bit wide field to encode 2048 messages rw 000_0000_0001 register 8h ? link partner next page ability 8.15 next page 1 = additional next page(s) will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = able to act on the information 0 = not able to act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic zero 0 = previous value of transmitted link code word equal to logic one ro 0 8.10:0 message field ro 000_0000_0000 register 10h ? digital reserved control 10.15:5 reserved rw 0000_0000_000 10.4 pll off 1 = turn pll off automatically in edpd mode. 0 = keep pll on in edpd mode. see also register 18h, bit [11] for edpd mode. rw 0 10.3:0 reserved rw 0000 register 11h ? afe control 1 11.15:6 reserved rw 0000_0000_00 11.5 slow oscillator mode enable slow oscillator mode is used to disconnect the input reference crystal/clock on the xi pin and select the on-chip slow oscillator when the ksz8021/31rnl device is not in use after power-up. 1 = enable 0 = disable this bit automatically sets software power down to the analog side when enabled. rw 0 11.4:0 reserved rw 0_0000 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 29 m9999-082710-1.0 register descrip tion (continued) address name description mode (1) default register 15h ? rxer counter 15.15:0 rxer counter receive error counter for symbol error frames ro/sc 0000h register 16h ? operation mode strap override 16.15:11 reserved rw 0000_0 16.10 reserved ro 0 16.9:7 reserved rw 00_0 16.6 rmii b-to-b override 1 = override strap-in for rmii back-to-back mode (set also bit 1 of this register to 1) rw 0 16.5 nand tree override 1 = override strap-in for nand tree mode rw 0 16.4:2 reserved rw 0_00 16.1 rmii override 1 = override strap-in for rmii mode rw 1 16.0 reserved rw 0 register 17h ? operation mode strap status 17.15:13 phyad[2:0] strap-in status [000] = strap to phy address 0 [011] = strap to phy address 3 the ksz8021/31rnl supports only phy addresses 0x0h and 0x3h only. ro 17.12:2 reserved ro 17.1 rmii strap-in status 1 = strap to rmii mode ro 17.0 reserved ro register 18h ? expanded control 18.15:12 reserved rw 0000 18.11 edpd disabled energy detect power down (edpd) mode 1 = disable 0 = enable see also register 10h, bit [4] for pll off. rw 1 18.10:0 reserved rw 000_0000_0000 register 1bh ? interrupt control/status 1b.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 30 m9999-082710-1.0 register descrip tion (continued) address name description mode (1) default 1b.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 1b.10 link down interrupt enable 1= enable link down interrupt 0 = disable link down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link up interrupt enable 1 = enable link up interrupt 0 = disable link up interrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occurred ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occurred ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occur ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occur ro/sc 0 1b.3 link partner acknowledge interrupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occur ro/sc 0 1b.2 link down interrupt 1 = link down occurred 0 = link down did not occur ro/sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occur ro/sc 0 1b.0 link up interrupt 1 = link up occurred 0 = link up did not occur ro/sc 0 register 1dh ? linkmd ? control/status 1d.15 cable diagnostic test enable 1 = enable cable diagnostic test. after test has completed, this bit is self-cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 1d.14:13 cable diagnostic test result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test has failed ro 00 1d.12 short cable indicator 1 = short cable (<10 meter) has been detected by linkmd ? . ro 0 1d.11:9 reserved rw 000 1d.8:0 cable fault counter distance to fault ro 0_0000_0000 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 31 m9999-082710-1.0 register descrip tion (continued) address name description mode (1) default register 1eh ? phy control 1 1e.15:10 reserved ro 0000_00 1e.9 enable pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0 1e.8 link status 1 = link is up 0 = link is down ro 0 1e.7 polarity status 1 = polarity is reversed 0 = polarity is not reversed ro 1e.6 reserved ro 0 1e.5 mdi/mdi-x state 1 = mdi-x 0 = mdi ro 1e.4 energy detect 1 = presence of signal on receive differential pair 0 = no signal detected on receive differential pair ro 0 1e.3 phy isolate 1 = phy in isolate mode 0 = phy in normal operation rw 0 1e.2:0 operation mode indication [000] = still in auto-negotiation [001] = 10base-t half-duplex [010] = 100base-tx half-duplex [011] = reserved [100] = reserved [101] = 10base-t full-duplex [110] = 100base-tx full-duplex [111] = reserved ro 000 register 1fh ? phy control 2 1f:15 hp_mdix 1 = hp auto mdi/mdi-x mode 0 = micrel auto mdi/mdi-x mode rw 1 1f:14 mdi/mdi-x select when auto mdi/mdi-x is disabled, 1 = mdi-x mode transmit on rxp,rxm (pins 4,3) and receive on txp,txm (pins 6,5) 0 = mdi mode transmit on txp,txm (pins 6,5) and receive on rxp,rxm (pins 4,3) rw 0 1f:13 pair swap disable 1 = disable auto mdi/mdi-x 0 = enable auto mdi/mdi-x rw 0 1f.12 reserved rw 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit bypasses the control logic and allow transmitter to send pattern even if there is no link. rw 0 micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 32 m9999-082710-1.0 register descrip tion (continued) address name description mode (1) default 1f.10 power saving 1 = enable power saving 0 = disable power saving rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.7 rmii reference clock select 1 = rmii ? 50mhz clock mode; clock input to xi (pin 8) is 50mhz 0 = rmii ? 25mhz clock mode; clock input to xi (pin 8) is 25mhz rw 1 (for KSZ8021RNL) 0 (for ksz8031rnl) 1f.6 reserved rw 0 1f.5:4 led mode [00] = led0 : link/activity [01] = led0 : link [10], [11] = reserved rw 00 1f.3 disable transmitter 1 = disable transmitter 0 = enable transmitter rw 0 1f.2 remote loop-back 1 = remote (analog) loop back is enable 0 = normal mode rw 0 1f.1 reserved rw 0 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 note: 1. rw = read/write. ro = read only. sc = self-cleared. lh = latch high. ll = latch low. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 33 m9999-082710-1.0 absolute maximum ratings (1) supply voltage (v dd_1.2 ) .................................................. ? 0.5v to +1.8v (v ddio, v dda_3.3 ) ....................................... ? 0.5v to +4.0v input voltage (all i nputs) .............................. ? 0.5v to +4.0v output voltage (all outputs) ......................... ? 0.5v to +4.0v lead temperature (solde ring, 10sec .) ....................... 260c storage temperature (t s ) ......................... ? 55c to +150c operating ratings (2) supply voltage (v ddio_3.3, v dda_3.3 ) .......................... +3.135v to +3.465v (v ddio_2.5 )........................................ +2.375v to +2.625v (v ddio_1.8 )........................................ +1.710v to +1.890v ambient temperature (t a , commercial)...................................... 0c to +70c (t a , industrial) ...................................... ? 40c to +85c maximum junction temperature (t j max) ................. 125c thermal resistance ( ja ) ....................................49.22c/w thermal resistance ( jc ) ....................................25.65c/w electrical characteristics (3) symbol parameter condition min. typ. max. units supply current (v ddio ,v dda_3.3 = 3.3v) (4) i dd1 10base-t full-duplex traffic @ 100% utilization 45 ma i dd2 100base-tx full-duplex traffic @ 100% utilization 49 ma i dd3 power saving mode ethernet cable disc onnected (reg. 1f.10 = 1) 30 ma i dd4 power down mode software power down (reg. 0.11 = 1) 3.0 ma cmos level inputs v ddio = 3.3v 2.0 v ddio = 2.5v 1.8 v ih input high voltage v ddio = 1.8v 1.3 v v ddio = 3.3v 0.8 v ddio = 2.5v 0.7 v il input low voltage v ddio = 1.8v 0.5 v i in input current v in = gnd ~ vddio -10 10 a cmos level outputs v ddio = 3.3v 2.4 v ddio = 2.5v 2.0 v oh output high voltage v ddio = 1.8v 1.5 v v ddio = 3.3v 0.4 v ddio = 2.5v 0.4 v ol output low voltage v ddio = 1.8v 0.3 v |i oz | output tri-state leakage 10 a led output i led output drive current led0 pin 8 ma strapping pins v ddio = 3.3v 29 43 76 v ddio = 2.5v 37 59 102 pu internal pull-up resistance v ddio = 1.8v 57 100 187 k? v ddio = 3.3v 27 43 76 v ddio = 2.5v 35 60 110 pd internal pull-down resistance v ddio = 1.8v 55 100 190 k? micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 34 m9999-082710-1.0 electrical characteristics (3) (continued) symbol parameter condition min. typ. max. units 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 termination across differential output 2 % rise/fall time 3 5 rise/fall time imbalance 0 0.5 duty-cycle distortion + 0.25 ns t r , t f overshoot 5 % v set reference voltage of iset 0.65 v output jitter peak-to-peak 0.7 1.4 ns 10base-t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 termination across differential output 2.2 2.8 v jitter added peak-to-peak 3.5 ns t r , t f rise/fall time 25 ns 10base-t receive v sq squelch threshold 5mhz square wave 400 mv ref_clk output 50mhz rmii clock output jitter peak-to-peak (applies to rmii ? 50mhz clock mode only) 600 ps notes: 1. exceeding the absolute maximum rating may damage the device. stresses greater than the absolute maximum rating may cause per manent damage to the device. operation of the device at these or any other conditions above t hose specified in the operating sections of this specification is not implied. maximum conditions for ex tended periods may affect reliability. 2. the device is not guaranteed to function outside its operating rating. 3. t a = 25 c. specification is for packaged product only. 4. current consumption is for the single 3.3v supply ksz8021/31rnl device only, and includes the transmit driver current and the 1.2v supply voltage (v dd_1.2 ) that are supplied by the ksz8021/31rnl. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 35 m9999-082710-1.0 timing diagrams rmii timing figure 8. rmii timing ? data received from rmii figure 9. rmii timing ? data input to rmii timing parameter description min. typ. max. unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 7 9 13 ns table 7. rmii timing parameters ? ksz8021/31rnl (25mhz input to xi pin, 50mhz output from ref_clk pin) timing parameter description min. typ. max. unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 8 ns t od output delay 9 13 15 ns table 8. rmii timing parameters ? ksz8021/31rnl (50mhz input to xi pin) micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 36 m9999-082710-1.0 auto-negotiation timing figure 10. auto-negotiation fast link pulse (flp) timing timing parameter description min. typ. max. units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per flp burst 17 33 table 9. auto-negotiation fast link pulse (flp) timing parameters micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 37 m9999-082710-1.0 mdc/mdio timing figure 11. mdc/mdio timing timing parameter description min. typ. max. unit t p mdc period 400 ns t 1md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay from rising edge of mdc * [can vary with mdc clock frequency] * ns table 10. mdc/mdio timing parameters micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 38 m9999-082710-1.0 reset timing the ksz8021/31rnl reset timing requirement is summarized in figure 12 and table 11. figure 12. reset timing parameter description min. max. units t vr supply voltage (v ddio, v dda_3.3 ) rise time 300 s t sr stable supply voltage (v ddio, v dda_3.3 ) to reset high 10 ms t cs configuration setup time 5 ns t ch configuration hold time 5 ns t rc reset to strap-in pin output 6 ns table 11. reset timing parameters the supply voltage (v ddio, and v dda_3.3 ) power-up waveform should be monotonic, and the 300s minimum rise time is from 10% to 90%. after the de-assertion of reset, it is recommended to wait a minimum of 100s before st arting programming on the miim (mdc/mdio) interface. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 39 m9999-082710-1.0 reset circuit the following reset circuit is recommended for powering up the ksz8021/31rnl if reset is triggered by the power supply. figure 13. recommended reset circuit the following reset circuit is recommended for applications w here reset is driven by another device (e.g., cpu or fpga). at power-on-reset, r, c and d1 provide the necessary ra mp rise time to reset the ksz8021/31rnl device. the rst_out_n from cpu/fpga provides the warm reset after power up. figure 14. recommended reset circuit for interfacing with cpu/fpga reset output micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 40 m9999-082710-1.0 reference circuit for led strapping pin the pull-up, float and pull-down reference circuits for the led0/anen_speed strappi ng pin are shown in figure 15 for 3.3v and 2.5v vddio. figure 15. reference circuits for led strapping pin for 1.8v vddio, led indication support is not recommen ded due to the low voltage. wit hout the led indicator, the anen_speed strapping pin is functional with 4.7k pull-up to 1.8v vddio or float for a value of ?1?, and with 1.0k pull- down to ground for a value of ?0?. micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 41 m9999-082710-1.0 magnetics specification a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common-mode chokes is recommended for exceeding fcc requirements. tables 12 and 13 list recommended magnetic characteri stics and qualified magnet ics for the ksz8021/31rnl. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350 h 100mv, 100khz, 8ma insertion loss (max.) ? 1.0db 100khz ? 100mhz hipot (min.) 1500vrms table 12. magnetics selection criteria magnetic manufacturer part number auto mdi-x number of port bel fuse s558-5999-u7 yes 1 bel fuse (mag jack) si-46001-f yes 1 bel fuse (mag jack) si-50170-f yes 1 delta lf8505 yes 1 lankom lf-h41s-1 yes 1 pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 tdk (mag jack) tla-6t718a yes 1 table 13. qualified single port 10/100 magnetics reference clock ? conn ection and selection a crystal or external clock source, such as an oscillator, is used to provide the reference clock for the ksz8021/31rnl. for the ksz8021/31rnl in rmii ? 25mhz clock mode, the refere nce clock is 25mhz. the reference clock connections to xi (pin 8) and xo (pin 7), and the reference clock se lection criteria are provided in figure 16 and table 14. figure 16. 25mhz crystal / oscillator reference clock connection micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 42 m9999-082710-1.0 characteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm table 14. 25mhz crystal / refe rence clock selection criteria for the ksz8021/31rnl in rmii ? 50mhz clock mode, the refere nce clock is 50mhz. the reference clock connection to xi (pin 8), and the reference clock selection criteria are provided in figure 17 and table 15. figure 17. 50mhz oscillator reference clock connection characteristics value units frequency 50 mhz frequency tolerance (max) 50 ppm table 15. 50mhz oscillator / refe rence clock selection criteria micrel, inc. KSZ8021RNL / ksz8031rnl august 2010 43 m9999-082710-1.0 package information 24-pin (4mm x 4mm) qfn micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to t he accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for it s use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether expre ss, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, mi crel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including l iability or warranties relating to fitness for a particular purpose, merchantability, or infringement of an y patent, copyright or other intellectual p roperty right micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk a nd purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2010 micrel, incorporated. |
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